In many electronic systems, data may be transmitted or retrieved without any timing reference. For example, in optical communications, a stream of data may flow over a fiber without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Therefore, the clock or timing information must be recovered from the data at the receiver using clock and data recovery (CDR) circuits. With the rapid growth of electrical and optical link capability, CDR circuits may require operating at high speeds such as tens of gigabits per second (Gbits/second).
Further, clock and data recovery (CDR) circuits are important for modern transceiver systems to reduce jitter and improve signal quality. Phase-locked-loop (PLL)-based CDR is widely employed in monolithic implementations of continuous-mode CDR circuits. Due to the narrow frequency acquisition range of PLL, most CDR implementations require external reference clock sources. However, when such a reference clock source is not easily available, e.g. in retimer applications, referenceless CDR circuits may be necessary, which can perform both frequency acquisition and phase locking solely based on the incoming data stream.
Several different approaches have been developed to realize referenceless CDR, including dedicated frequency-locking and phase-locking loops, a conditionally closed loop, rotational frequency detectors, half-rate phase and frequency detector (PFD) and V/I converter, and the FD based on transition counting mechanisms.